View SIL164_3151426.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? technology sii 164 panellink panellink panellink panellink transmitter data sheet document # sii-ds-0021-d.doc www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d ii silicon image, inc. sii -ds-0021-d september 2002 application information to obtain the most updated application notes and other useful information for your design, please visit the silicon image web site at www.siliconimage.com or contact your local silicon image sales office. copyright notice this manual is copyrighted by silicon image, inc. do not reproduce, transform to any other format, or send/transmit any part of this documentation without the expressed written permission of silicon image, inc. trademark acknowledgment silicon image, the silicon image logo, panellink ? and the panellink ? digital logo are registered trademarks of silicon image, inc. tmds tm is a trademark of silicon image, inc. vesa ? , fpd tm are trademarks of the video electronics standards association. i 2 c is a trademark of philips semiconductor. all other trademarks are the property of their respective holders. disclaimer this document provides technical information for the user. silicon image, inc. reserves the right to modify the information in this document as necessary. the customer should make sure that they have the most recent data sheet version. silicon image, inc. holds no responsibility for any errors that may appear in this document. customers should take appropriate action to ensure their use of the products does not infringe upon any patents. silicon image, inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. all information contained herein is subject to change without notice. revision history revision date comment sii-ds-0021-a 01/99 full release sii-ds-0021-b 03/99 internal revision b release sii-ds-0021-c 04/02 new format. i 2 c programming andstrapping mode description,tft mapping and design recommendations, pin names isel/rst changed to isel/rst# and pd to pd#. sii-ds-0021-d 09/02 included pb-free package. added de-skew range. corrected pd# pin number. ? 2002 silicon image, inc. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet iii sii- ds-0021-d table of contents general description ............................................................................................................ ............................ 1 features ....................................................................................................................... ............................... 1 sii 164 pin diagram.................................................................................................................... .................... 1 functional description ......................................................................................................... ........................... 2 panellink tmds digital core .................................................................................................... ................. 2 i 2 c interface and registers ...................................................................................................... ................... 2 data capture logic ............................................................................................................. ........................ 3 electrical specifications ...................................................................................................... ............................ 4 absolute maximum conditions.................................................................................................... ................ 4 normal operating conditions.................................................................................................... .................. 4 digital i/o specifications ..................................................................................................... ........................ 4 dc specifications .............................................................................................................. .......................... 5 ac specifications .............................................................................................................. .......................... 6 input timing diagrams .......................................................................................................... ...................... 7 pin descriptions ............................................................................................................... ............................... 9 input pins ..................................................................................................................... ............................... 9 configuration pins ............................................................................................................. ........................ 10 input voltage reference pin.................................................................................................... ...................11 power management pins .......................................................................................................... .................11 differential signal data pins.................................................................................................. .....................11 reserved pins .................................................................................................................. ..........................11 power and ground pins .......................................................................................................... ...................11 i 2 c registers.................................................................................................................... ............................. 12 i 2 c register mapping ............................................................................................................. ................... 12 i 2 c register definitions ......................................................................................................... .................... 13 i 2 c slave interface and address .................................................................................................. ............. 15 data de-skew feature ........................................................................................................... ................... 16 data latching modes ............................................................................................................ .................... 17 i 2 c programming sequence ......................................................................................................... ............ 18 enabling hot plug detection mode ............................................................................................... ............ 18 non i 2 c mode configuration ........................................................................................................... .......... 19 tft panel data mapping......................................................................................................... ..................... 21 design recommendations......................................................................................................... ................... 24 1.5v to 3.3v i 2 c bus level-shifting........................................................................................................... 24 voltage ripple regulation ...................................................................................................... ................... 25 decoupling capacitors .......................................................................................................... .................... 26 series damping resistors on outputs ............................................................................................ .......... 27 differential trace routing..................................................................................................... ..................... 27 package dimensions and marking specification................................................................................... ....... 29 ordering information........................................................................................................... .......................... 29 www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d iv list of tables table 1. data de-skew estimated values ......................................................................................... ........... 16 table 2. sample programming sequence for sii 164................................................................................... 18 table 3. non i 2 c strapping mode options .................................................................................................... 20 table 4. one pixel/clock input/output tft mode - vesa p&d and fpdi-2 tm compliant........................... 21 table 5. 24-bit one pixel/clock input with 24-bit two pixels/clock output tft mode ................................ 22 table 6. 18-bit one pixel/clock input with 18-bit two pixels/clock output tft mode ................................ 23 table 7. recommended components for bypass and decoupling circuits ................................................. 26 list of figures figure 1. pin diagram for sii 164 ................................................................................................................... 1 figure 2. functional block diagram............................................................................................. ................... 2 figure 3. clock cycle high/low times ........................................................................................... ................ 7 figure 4. low swing differential times ......................................................................................... ................. 7 figure 5. isel/rst# minimum timing ............................................................................................. .............. 7 figure 6. input data setup/hold time to idck................................................................................... ............ 8 figure 7. vsync, hsync and ctl[3:1] delay time from de....................................................................... 8 figure 8. de high and low times ................................................................................................ .................. 8 figure 9. i 2 c data valid delay (driving read cycle data) ............................................................................... 8 figure 10. i 2 c byte read .................................................................................................................... .......... 15 figure 11. i 2 c byte write ................................................................................................................... ........... 15 figure 12. sii 164 data de-skew feature timing......................................................................................... 16 figure 13. 12 bit input data latching.......................................................................................... .................. 17 figure 14. 24 bit input data latching.......................................................................................... .................. 17 figure 15. non i 2 c mode schematic example ............................................................................................. 19 figure 16. i 2 c bus voltage level-shifting using fairchild ndc7002n ......................................................... 24 figure 17. i 2 c bus voltage level shifting using philips gtl 2010............................................................... 24 figure 18. voltage regulation using tl431...................................................................................... ............ 25 figure 19. voltage regulation using lm317 ...................................................................................... ........... 25 figure 20. decoupling and bypass capacitor placement ........................................................................... .26 figure 21. decoupling and bypass schematic ..................................................................................... ........ 26 figure 22. series input damping resistors for driving source ................................................................... .27 figure 23. example of incorrect differential signal routing .................................................................... ..... 27 figure 24. example of correct differential signal routing ...................................................................... ..... 28 figure 25. differential trace routing to dvi connector(top side view) ...................................................... 28 figure 26. 64-pin tqfp package dimensions (jedec code ms-026ed) .................................................. 29 www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink panellink panellink panellink transmitter september 200 2 data sheet 1 sii -ds-0021-d general description the sii 164 transmitter uses panellink ? digital technology to support displays ranging from vga to uxga resolutions (25 - 165mpps) in a single link interface. the sii 164 transmitter has a highly flexible interface with either a 12-bit mode (? pixel per clock edge) or 24-bit mode 1 pixel per clock edge input for true color (16.7 million) support. in 24-bit mode, the sii 164 supports single or dual edge clocking. in 12-bit mode, the sii164 supports dual edge single clocking or single edge dual clocking. the sii 164 can be programmed though an i 2 c interface. in addition the sii 164 also supports receiver and hot plug detection. panellink digital technology simplifies pc design by resolving many of the system level issues associated with high-speed mixed signal design, providing the system designer with a digital interface solution that is quicker to market and lower in cost. features ? scaleable bandwidth: 25 - 165mhz flexible ? graphics controller interface: 12-bit or 24-bit mode 1 pixel/clock inputs ? flexible input clocking: single clock single edge (24-bit), single clock dual edge (12-/24- bit), dual clock single edge (12-bit) ? i 2 c slave programming interface up to 100khz ? low voltage interface: 3.3v with option for 1.0 to 3.0v low voltage signal mode ? monitor detection supported through hot plug and receiver detection ? de-skewing option varies input clock to input data timing ? low power: 3.3v operation (120ma max.) and power down mode (1ma max.) ? cable distance support: over 5m with twisted pair and fiber-optics ready ? compliant with dvi 1.0 (dvi is backwards compliant with vesa ? p&d tm and dfp) ? standard and pb-free packages (see pg 29) sii 164 pin diagram vcc de vref hsync vsync ctl3/a3/dk3 ctl2/a2/dk2 ctl1/a1/dk1 edge/htplg pd# msen vcc isel/rst# dsel/sda bsel/scl gnd pgnd pvcc1 ext_swing agnd txc- txc+ avcc tx0- tx0+ agnd tx1- tx1+ avcc tx2- tx2+ vcc reserved dken d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 gnd pvcc2 d11 d10 d9 d8 d7 d6 idck- idck+ d5 d4 d3 d2 d1 d0 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 sii 164 64-pin tqfp (top view) agnd figure 1. pin diagram for sii 164 www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 2 functional description the sii 164 is a dvi 1.0 compliant panellink transmitter in a compact package. it provides 24 bits for data input to allow for panel support up to uxga resolution. figure 2 shows the functional blocks of the chip. registers & configuration logic block scl sda pd edge/htplg bsel/scl dsel/sda ctl/a/dk[3:1] i 2 c slave machine data capture logic block d[23:0] idck+ idck- vsync hsync txc+ tx0+ tx1+ tx2+ vref de msen panellink panellink panellink panellink digital core isel/rst ext_swin g dken a[3:1] figure 2. functional block diagram panellink tmds digital core the panellink tmds core encodes video information onto three tmds differential data lines and the differential clock. the video data is input by the data capture logic block, as a 12- or 24-bit bus, using one or two clocks with one or two edges per clock. an attached monitor may be sensed using the htplg pin or internally with receiver sense. this detected state may be output onto the msen pin. the device may be powered down using the pd# pin or with an internal register. the sii 164 is reset using the isel/rst# pin . a resistor tied to the ext_swing pin is used to control the tmds swing amplitude. i 2 c interface and registers the sii 164 uses a slave i 2 c interface, capable of running at 100khz. the slave i 2 c interface is not 5v tolerant. if the switching levels from the host are not 3.3v, then a voltage level shifter must be used. see figure 16 and figure 17 on page 24 for a system diagram. a connected display may be detected using the dvi hot plug signal, attached to the htplg pin; or with the receiver sense logic internal to the sii 164 . the state of the detection, or an interrupt signal indicating a change of state, may be sent to the msen pin. this is useful to the host controller monitoring the sii 164 . www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 3 sii -ds-0021-d data capture logic video data is input to the sii 164 by way of a 12-bit or 24-bit interface. the functionality of this interface is affected by several of the configuration register settings, as follows. ? bsel selects between 12-bit and 24-bit input bus widths. ? dsel selects between single-edge and dual-edge modes for the input clocks. ? edge selects between rising and falling edge on the input clocks. ? clk+ and clk- provide the one or two clocks required for latching the input data bus. ? the pd# input selects the chip power down mode and allows for disabling of the tmds outputs. the isel/rst# input resets the hdcp engine and internal registers and is asserted after power up and receipt of a stable input pixel clock. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 4 electrical specifications absolute maximum conditions absolute maximum conditions are defined as the worst case conditions the part will tolerate without sustaining damage. permanent device damage may occur if absolute maximum conditions are exceeded. proper operation under these conditions is not guaranteed. functional operation should be restricted to the conditions described under normal operating conditions. symbol parameter min typ max units v cc supply voltage 3.3v -0.3 4.0 v v i input voltage -0.3 v cc + 0.3 v v o output voltage -0.3 v cc + 0.3 v t j junction temperature (with power applied) 125 c t stg storage temperature -65 150 c normal operating conditions symbol parameter min typ max units v cc supply voltage 3.0 3.3 3.6 v v ccn supply voltage noise 100 mv p-p t a ambient temperature (with power applied) 0 25 70 c ja thermal resistance (junction to ambient) 1 64 c/w note 1. airflow at 0m/s. digital i/o specifications under normal operating conditions unless otherwise specified. symbol parameter conditions min typ max units v ih high swing high-level input voltage v ref = v cc 2.0 v v il high swing low-level input voltage v ref = v cc 0.8 v v ddq 2 low swing voltage 1 3.0 v v sh low swing high-level input voltage v ref = v ddq /2 v ddq /2 + 300mv v v sl low swing low-level input voltage v ref = v ddq /2 v ddq /2 ? 100mv v v cinl input clamp voltage 1 i cl = -18ma gnd -0.8 v v cipl input clamp voltage 1 i cl = 18ma vcc + 0.8 v i il input leakage current -10 10 a v ih high swing high-level input voltage v ref = v cc 2.0 v notes 1. guaranteed by design. voltage undershoot or overshoot cannot exceed absolute maximum conditions 2. vddq defines the maximum voltage level of low swing input. it is not an actual input voltage. chip characterization for low swing operation is performed at 1.5v only. voltage level of low swing input should never exceed absolute maximum rating. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 5 sii -ds-0021-d dc specifications under normal operating conditions unless otherwise specified. symbol parameter conditions min typ max units v od differential voltage single ended peak to peak amplitude r load = 50 ? , r ext_swing = 510 ? 510 550 590 mv v doh differential high-level output avcc v voltage 1 i dos differential output short circuit current 1 v out = 0 v 5 a i pd# power-down current 2 0.2 1.0 ma i cct transmitter supply current idck= 165 mhz, 1-pixel/clock mode, r ext_swing = 510 ? , ivcc = vcc, worst case pattern 3 85 120 ma notes 1. guaranteed by design. 2. assumes all inputs to the transmitter are not toggling. 3. black and white checkerboard pattern, each checker is one pixel wide. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 6 ac specifications under normal operating conditions unless otherwise specified. symbol parameter conditions min typ max units figure t cip idck period, 1-pixel/clock 6 40 ns figure 3 f cip idck frequency, 1-pixel/clock 25 165 mhz t cih idck high time at 165mhz 2.0 ns figure 3 t cil idck low time at 165mhz 2.0 ns figure 3 t ijit worst case idck clock jitter 2,3 2 ns t sidf data, de, vsync, hsync setup time to idck falling edge (default de-skew setting) single edge (dsel = 0, edge = 0) 1.0 ns figure 6 t hidf data, de, vsync, hsync hold time from idck falling edge (default de-skew setting) single edge (dsel = 0, edge = 0) 0.9 ns figure 6 t sidr data, de, vsync, hsync setup time to idck rising edge 1 (default de-skew setting) single edge (dsel = 0, edge = 1) 1.0 ns figure 6 t hidr data, de, vsync, hsync hold time from idck rising edge 1 (default de-skew setting) single edge (dsel = 0, edge = 1) 0.9 ns figure 6 t sid data, de, vsync, hsync setup time to idck falling/rising edge 1 (default de-skew setting) dual edge (dsel = 1, bsel = 0) 0.6 ns t hid data, de, vsync, hsync hold time from idck falling/rising edge 1 (default de-skew setting) dual edge (dsel = 1, bsel = 0) 1.3 ns t ddf vsync, hsync delay from de falling edge 1 1t cip ns figure 7 t ddr vsync, hsync delay to de rising edge 1 1t cip ns figure 7 t hde de high time 1 8191t cip ns figure 8 t lde de low time 1 128t cip ns figure 8 t step de-skew step size increment dken = 1 260 ps t reset duration of reset signal low required for valid reset 10 s figure 5 c l = 10pf 700 ns t i2cdvd sda data valid delay from scl high to low transition 3 c l = 400pf 2000 ns figure 9 s hlt differential swing high-to-low transition time r load = 50 ? , r ext_swing = 510 ? 170 200 230 ps figure 4 s lht differential swing low-to-high transition time r load = 50 ? , r ext_swing = 510 ? 170 200 230 ps figure 4 notes 1. guaranteed by design. 2. actual jitter tolerance may be higher depending on the frequency of the jitter. 3. all standard mode i 2 c (100khz) timing requirements are guaranteed by design. fast mode i 2 c (400khz) timing requirements are guaranteed at 10pf loading. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 7 sii -ds-0021-d input timing diagrams t cih t cil t cip 2.0 v 0.8 v 0.8 v 2.0 v 2.0 v figure 3. clock cycle high/low times figure 4. low swing differential times isel/rst# vcc t reset figure 5. isel/rst# minimum timing s lht 20% v od 80% v od s hlt www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 8 figure 6. input data setup/hold time to idck figure 7. vsync, hsync and ctl[3:1] delay time from de de t lde t hde 0.8 v 2.0 v 0.8 v 2.0 v figure 8. de high and low times figure 9. i 2 c data valid delay (driving read cycle data) d[23:0], de, hsync,vsync idck t sidf t hidf t sidr t hidr 50 % 50 % 50 % 50 % t ddr t ddf de vsync, hsync, ctl[3:1] 0.8 v 0.8 v 0.8 v 0.8 v de vsync, hsync, ctl[3:1] scl ti2 i2cdvd sda www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 9 sii -ds-0021-d pin descriptions input pins pin name pin # type description d[23:12] 36-47 in top half of 24-bit pixel bus. when bsel = high , this bus inputs the top half of the 24-bit pixel bus. when bsel = low, these bits are not used to input pixel data. in this mode, the state of d[23:16] is input to the i 2 c register cfg. this allows 8-bits of user configuration data to be read by the graphics controller through the i 2 c interface (see i 2 c register definition). when not used d[23:16] should be tied to ground. d[15:12] are reserved for sii use only and should be tied to gnd. d[11:0] 50- 55, 58-63 in bottom half of 24-bit pixel bus / 12-bit pixel bus input. when bsel = high , this bus inputs the bottom half of the 24-bit pixel bus. when bsel = low , this bus inputs ? a pixel (12-bits) at every latch edge (both falling and/or rising) of the clock. idck+ 57 in input data clock +. this clock is used for all input modes. idck- 56 in input data clock ?. this clock is only used in 12-bit mode when dual edge clocking is turned off (dsel = low). it is used to provide the odd latching edges for dual clock single edge. if bsel = high or dsel = high , this pin is unused and should be tied to gnd. de 2 in input data enable. this signal qualifies the active data area. de is always required by the transmitter and must be high during active display time and low during blanking time. hsync 4 in horizontal sync input control signal vsync 5 in vertical sync input control signal. ctl1/a1/dk1 ctl2/a2/dk2 ctl3/a3/dk3 8 7 6 in the use of these multi-function inputs depends on the settings of isel/rst# and dken. these inputs are regular high-swing 3.3v cmos level inputs. these pins contain weak pull- down resistors so that if left unconnected, they will be low. when isel/rst# = low, dken = low general purpose input ctl[3:1] pins are active, for backward compatibility. these pins must be used to send dc signals only during the blanking time. when isel/rst# = low, dken = high dk[3:1] are active, these inputs are used to select the de-skewing setting for the input bus. when isel/rst# = high, dken = high a[3:1] are active, these bits are used to set the lower 3 bits of the i 2 c device address. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 10 pin descriptions (cont?d) configuration pins pin name pin # type description msen 11 out monitor sense. this pin is an open collector output. the behavior of this output depends on whether i 2 c interface active: i 2 c bus inactive (isel/rst# = low) high level indicates a powered on receiver is detected at the differential outputs. a low level indicates a powered on receiver is not detected. i 2 c bus is enabled (isel/rst# = high) the output is programmable through the i 2 c interface (see i 2 c register definitions). an external 5k pull-up resistor to vddq is required on this pin. isel/rst# 13 in i 2 c interface select. isel/rst#=high , i 2 c interface is active. isel/rst#=low , i 2 c is inactive and the chip configuration is read from the configuration strapping pins. this pin also acts as an asynchronous reset to the i 2 c interface controller. the reset is active when this input is held low. note : when the i 2 c interface is active, dken must be set high. bsel/scl 15 in input bus select / i 2 c clock. this pin is an open collector input. if i 2 c bus is enabled (isel/rst# = high), then this pin is the i 2 c clock input. if the i 2 c is disabled (isel/rst# = low), then this pin selects the input bus width. input bus select: high selects 24-bit input mode low selects 12-bit input mode dsel/sda 14 in/out dual edge clock select / i 2 c data. this pin is an open collector input/output. if i 2 c bus is enabled (isel/rst# = high), then this pin is the i 2 c data line. if the i 2 c bus is disabled (isel/rst# = low), then this pin selects whether single clock dual edge is used. dual edge clock select: when high, idck+ latches input data on both falling and rising clock edges. when low, idck+/idck- latches input data on only falling or rising clock edges. in 24-/12-bit mode: if high (dual edge), idck+ is used to latch data on both falling and rising edges. if low (single edge), idck+ latches 1 st half data and idck- latches 2 nd half data. edge/ htplg 9 in edge select / hot plug input. if the i 2 c bus is enabled (isel/rst# = high), then this pin is used to monitor the ?hot plug? detect signal (please refer to the dvi tm or vesa ? p&d tm and dfp standards). this input is only 3.3v tolerant and has no internal de-bouncer circuit. if i 2 c bus is disabled (isel/rst# = low), then this pin selects the clock edge that will latch the data. how the edge setting works depends on whether dual or single edge latching is selected: dual edge mode (dsel = high) edge = low, the primary edge (first latch edge after de is asserted) is the falling edge. edge = high, the primary edge (first latch edge after de is asserted) is the rising edge. note: in 24-bit single clock dual edge mode, edge is ignored. single edge mode (dsel = low) edge = low, the falling edge of the clock is used to latch data. edge = high, the rising edge of the clock is used to latch data. dken 35 in de-skewing enable. i 2 c mode (isel/rst# = high) dken pin must be set to high. dk[3:1] pins are ignored and the de-skewing increments are selected through the i 2 c interface (see the i 2 c register definitions). non i 2 c mode (isel/rst# = low) dken = low, then default de-skewing setting is used. dken = high, then dk[3:1] is used as the de-skewing setting. the de-skewing increments are t step . please see data de-skew feature for an illustration. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 11 sii -ds-0021-d pin descriptions (cont?d) input voltage reference pin pin name pin # type description vref 3 analog in input reference voltage. selects the swing range of the digital inputs, which include only d[23:0], idck+, idck-, de, vsync, and hsync. input pins scl and sda, rst, bsel, dsel, edge and pd# require 3.3v high swing signals and are not changed by the vref input. to set the digital inputs to 3.3v high voltage swing, vref must be set to 3.3v. to set the digital inputs to low voltage swing, vref must be set to ? of vddq where vddq is swing level of input signal. thus for dvo mode(1.5v low voltage swing) vref should be set to 0.75v and bsel=low. power management pins pin name pin # type description pd# 10 in power down ( active low ). a high level indicates normal operation. a low level indicates power down mode. in power down mode the analog core is disabled and output buffers/pins are tri-stated however the input buffer/pins and i 2 c block for read and write are active. pd# pin is disabled during i 2 c mode. pd# should be tied low during i 2 c mode. differential signal data pins pin name pin # type description tx0+ tx0- tx1+ tx1- tx2+ tx2- 25 24 28 27 31 30 analog analog analog analog analog analog tmds low voltage differential signal input data pairs. these pins are tri-stated when pd# is pulled low. txc+ txc- 22 21 analog analog tmds low voltage differential signal input clock pair. these pins are tri-stated when pd# is pulled low. ext_swing 19 analog voltage swing adjust. a resistor should tie this pin to avcc. this resistor sets the amplitude of the voltage swing. a smaller resistor value sets a larger voltage swing and vice versa. for remote display applications a 510 ? resistor is recommended. while for notebook computers 680 ? is recommended to ensure voltage swing is not overdriven over a short cable distance. reserved pins pin name pin # type description reserved 34 in must be tied low for normal operation. power and ground pins pin name pin # type description vcc 1,12,33 power digital vcc, must be set to 3.3v nominal. gnd 16,48,64 ground digital gnd. avcc 23,29 power analog vcc, must be set to 3.3v nominal. agnd 20,26,32 ground analog gnd. pvcc1 18 power primary pll analog vcc, must be set to 3.3v nominal. pvcc2 49 power filter pll analog vcc, must be set to 3.3v nominal. pgnd 17 ground pll analog gnd. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 12 i 2 c registers i 2 c register mapping addr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 vnd_idl (ro) 0x01 vnd_idh (ro) 0x02 dev_idl (ro) 0x03 dev_idh (ro) 0x04 dev_rev (ro) 0x05 rsvd[7:0] 0x06 frq_low (ro) 0x07 frq_high (ro) 0x08 rsvd[1:0] ven (r/w) hen (r/w) dsel (rw) bsel (rw) edge (rw) pd (rw) 0x09 vlow (ro) msel[2:0] (rw) tsel (rw) rsen (ro) htplg (ro) mdi (rw) 0x0a dk[3:1] (rw) dken (rw) ctl[3:1] (rw) rsvd 0x0b cfg[7:0] 4 (ro) 0x0c 7 scnt (rw) rsvd pllf[3:1] (rw) pfen (rw) 0x0d rsvd[3:0] rsvd[3:0] 0x0e rsvd[7:0] 0x0f rsvd[7:0] notes 1. all values are bit 7(msb) and bit 0(lsb). 2. registers that can be written and read from are listed as (r/w) while registers that can be read only are listed with (ro). 3. actual jitter tolerance may be higher depending on the frequency of the jitter. 4. contents of this register are dependent on the status of pins d[23:16]. 5. after the reset signal is deasserted in i 2 c mode, only pd and msel have a default value or can retain their programmed value set before the reset. all other registers do not have a default value or retain their value after a reset. as such all required registers other than pd and msel must reinitialized in i 2 c mode after being powered up or reset. 6. registers listed as rsvd are reserved and for silicon image, inc use only. 7. 0x0c is also called the vdjk register. default setting for the vdjk register 0x0c is 89h, which is optimum for most applications. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 13 sii -ds-0021-d i 2 c register definitions register name access description vnd_idl ro vendor id low byte (01h) vnd_idh ro vendor id high byte (00h) dev_idl ro device id low byte (06h) dev_idh ro device id high byte (00h) dev_rev ro device revision (00h) frq_low ro low frequency limit at 1-pixel/clock mode (mhz) (19h) frq_high ro high frequency limit at 1-pixel/clock mode max frequency minus 65mhz (mhz) (64h) pd rw power down mode (same function as pd# pin) 0 ? power down (default after reset) 1 ? normal operation edge rw edge select (same function as edge pin) 0 ? input data is falling edge latched (falling edge latched first in dual edge mode) 1 ? input data is rising edge latched (rising edge latched first in dual edge mode) bsel rw input bus select (same function as bsel pin) 0 ? input data bus is 12-bits wide 1 ? input data bus is 24-bits wide dsel rw dual edge clock select (same function as dsel pin) 0 ? input data is single edge latched 1 ? input data is dual edge latched hen rw horizontal sync enable: 0 ? hsync input is transmitted as fixed low 1 ? hsync input is transmitted as is ven rw vertical sync enable: 0 ? vsync input is transmitted as fixed low 1 ? vsync input is transmitted as is mdi rw monitor detect interrupt 0 ? detection signal has changed logic level (write one to this bit to clear) 1 ? detection signal has not changed state htplg ro hot plug detect input, the state of htplg pin can be read from this bit rsen ro receiver sense (only available for use in dc coupled systems) 0 ? active/powered receiver not detected 1 ? active/powered receiver detected tsel rw interrupt generation method 0 ? interrupt bit (mdi) is generated by monitoring rsen 1 ? interrupt bit (mdi) is generated by monitoring htplg msel[2:0] rw select source of the msen output pin 000 ? force msen outputs high (disabled ? default after reset) 001 ? outputs the mdi bit (interrupt) 010 ? output the rsen bit (receiver detect) 011 ? outputs the htplg bit (hot plug detect) 1xx ? reserved vlow ro this bit is a 1 if the vref setting 1 ? indicates high swing inputs 0 ? indicates low swing inputs ctl[3:1] rw general purpose inputs (same as ctl[3:1] pins) www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 14 i 2 c register definitions (cont?d) register name access description cfg[7:0] ro contains state of inputs d[23:16]. these pins can be used to provide user selectable configuration data through the i 2 c bus. only available in 12-bit mode pfen rw pll filter enable in the vdjk register. 1 ? to enable pll filter (recommended setting) 0 ? to disable pll filter pllf[3:1] rw set characteristics of pll filter in the vdjk register 100 ? recommended value scnt rw sync continuous 1 ? to enable (recommended setting) 0 ? to disable dk[3:1] rw de-skewing setting. increment 260psec. 000 ? 1 step -> minimum setup / maximum hold 001 ? 2 step 010 ? 3 step 011 ? 4 step 100 ? 5 step -> default (recommended setting) 101 ? 6 step 110 ? 7 step 111 ? 8 step -> maximum setup / minimum hold please see data de-skew feature for an illustration dken rw de-skewing enable through dk[3:1] bits. when dken pin is high via pin or set to 1, then de-skew is enabled. when set to 0 de-skew is disabled. please see data de- skew feature for an illustration. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 15 sii -ds-0021-d i 2 c slave interface and address the sii 164 slave state machine does not require an internal clock and support only byte read and write. page mode is not supported. the 7-bit binary address of the i 2 c machine is ?0111 a 3 a 2 a 1 r? where r =1 sets a read operation while r=0 sets a write operation. please see figure 10 for a byte read operation and figure 11 for a byte write operation. for more detailed information on i 2 c protocols please refer to i 2 c bus specification version 2.1 available from philips semiconductors inc. when isel/rst# = high and dken = high, pins 6,7,8 functions as a[3:1]. each pin can be set to high or low to select a desired i 2 c address for the sii 164. to set the sii 164 to 72h, tie pin 7 and 6 to ground and pull pin 8 to vcc via 2.2k resistor. the recommended setting is to tie pins 6,7 and 8 to ground to set ?000? or address 70h in i 2 c mode . s a 3 a 2 a 1 a c k s a 3 a 2 a 1 a c k a c k p slave address register address slave address data stop start start bus activity : sii 164 bus activity : master sda line figure 10. i 2 c byte read s a 3 a 2 a 1 a c k a c k p slave address address data stop start bus activity : sii 164 bus activity : master sda line a c k figure 11. i 2 c byte write www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 16 data de-skew feature the de-skew feature allows adjustment of the clock-to-data delay on the input of the sii 164 . when driven by a chip with clock and data timings which do not meet the setup and hold time requirements of an sii 164 , the de- skew register value can be modified to position the clock in the middle of the valid data time and meet the input setup and hold times. as shown in figure 12, changing the dk[3:1] value from 0b100 to 0b111 delays the internal clock by approximately 750ps to 900ps, increasing setup time and reducing hold time. this is useful when the input clock, idck, arrives too early. the default values for dk[3:1] are shown in table 1, along with approximate times per setting. note that the default is different when enabling i 2 c mode (isel/rst#=high) versus non-i 2 c mode (isel/rst#=low). positive values of t cd move the clock later, increasing setup time. negative values of t cd move the clock earlier, increasing hold time. where: t cd is the amount of setup/hold timing variation dk[3:1] is the setting of the de-skew configuration pins or i 2 c registers table 1. data de-skew estimated values dk[3:1] de-skew time t cd 111 +0.75ns to +0.90ns 110 +0.50ns to +0.70ns 101 +0.20ns to +0.35ns 100 0 default de-skew 011 -0.20ns to -0.35ns 010 -0.50ns to ?0.70ns 001 -0.75ns to ?0.90ns 000 -1.0ns to -1.2ns t cd clk+ clk- dk[3:1] 000 100 111 d[23:0], de, vsync, hsync, ctl[3:1] - t cd default figure 12. sii 164 data de-skew feature timing www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 17 sii -ds-0021-d data latching modes sii 164 can be set to different to operate in either 12 bit or 24 bit input mode. in either mode the sii 164 can be set to latch data at either rising or falling edge of the clock or support dual edge clocking mode. figure 13 illustrates the latching edge for a 12 bit data input ( bsel = 0 ) by changing dsel and edge option. clock edges represented by arrows signify the latching edge. for dual edge mode, the dark arrows indicate the primary latch edge. p 0 lp o h idck+ d[11:0] p 1 lp 1 hp n-1 hp n lp n h de idck+ idck- idck+ idck+ idck- dsel = 1 dsel = 0 dsel = 1 dsel = 0 edge = 1 edge = 0 l = low half pixel h = high half pixel first latch edge figure 13. 12 bit input data latching figure 14 illustrates the latching edge for a 24 bit data input ( bsel=1 ) with dsel and edge option. edge pin has no affect in 24-bit single clock dual edge mode. first latching edge p 0 d[23:0] p 1 p n-1 p n de dsel = 1, edge = 0 dsel = 1, edge = 1 idck+ idck+ dsel =0, edge = 1 idck+ dsel = 0, edge = 0 idck+ figure 14. 24 bit input data latching www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 18 i 2 c programming sequence to program the sii 164 in data latched on 12 bit mode dual edge clock with primary edge as the rising edge, de- skew enabled without hotplug and the following sample programming sequence listed in table 2 may be used. it is important to note that the suggested i 2 c address for sii 164 be set to x70h by tying a1, a2 and a3 to ground. table 2. sample programming sequence for sii 164 register(hex) value(hex) description 0x08 30 enable hen, ven, 1 st data latched on falling edge with pd low until all registers are programmed. 0x09 00 msen disabled. 0x0a 90 de-skew enabled with default 100 value. ctl is not used. 0x0c 89 scnt, pll filter enable and pll bandwidth filter set to default. 0x08 31 set pd to high after the registers above have been programmed. enabling hot plug detection mode as documented in the vesa digital flat panel standard, all monitors are required to support hot plug detection but support is optional for the host. the sii 164 supports the hot plug detect feature. in i 2 c mode, pin 9 functions as htplg input. it should be noted that the htplg pin on the sii 164 is only 3.3v tolerant therefore htplg voltage level from the dvi connector should be level shifted or clamped at 3.3v. when the voltage level at the htplg pin is 3.3v, the htplg bit will be set to 1. to output the htplg bit via the msen pin, register msel[2:0] should be programmed to 011. the sii 164 can also be programmed to enable the hot plug detection mode via the receiver sense function. in this mode, htplg pin is not required. by programming msel[2:0] to 010, sii 164 will output the rsen=1 bit though the msen pin when the sii 164 is connected to a powered receiver. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 19 sii -ds-0021-d non i 2 c mode configuration the sii 164 can be set to program itself at power up without writing any sii 164 registers via i 2 c. the sii 164 is extremely flexible and can be set to operate in any input format that can be set in i 2 c mode. in non i 2 c mode, specific configuration pins need to be strapped to either high or low to set the desired mode. figure 15 provides a schematic example of all the pins that can be configured to enable the various modes in non i 2 c mode. table 3 lists resistors to be stuffed for a specific mode. d4 r18 15k 3.3v r10 33k bsel d6 r11 33k 3.3v r6 330 edge d2 b dken a dk1 r8 33k r2 2.2k r15 0 r3 2.2k r12 330 d[11..0] 1.5v or vddq d10 r17 2.2k d8 r14 0 d1 d7 c r4 330 avcc r13 0 d9 dk3 dk2 d0 vref r19 15k r16 510 1% sil 164 3 6 7 8 9 10 13 14 15 19 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 58 59 60 61 62 63 vref dk3 dk2 dk1 edge/chg/sin pd isel/rst dsel/sda bsel/scl ext_res rsvd dken d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d5 pd r1 2.2k 3.3v d d11 r9 33k dsel d3 r7 33k r5 330 figure 15. non i 2 c mode schematic example www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 20 non i 2 c mode configuration (cont?d) isel/rst# and rsvd pins must always be tied to ground for non i 2 c mode. pd# must be tied high or the sii 164 will still be in power down mode when vcc is applied. in figure 15 block a corresponds to the upper 12 bits (d [23:12]) of the sii 164. when not in use, they should always be tied to ground. block b controls the input bus data width, dual edge clock select and edge select. idck- is only used in 12 bit mode. in 24 bit mode or dual edge clock select idck- should be tied to ground. block c controls the de-skew options. block d determines the input voltage level swing. a full description of each pin can be found in the pin description section of this document. table 3. non i 2 c strapping mode options mode block a block b block c block d 1. 24 bit 1 2. single clock 3. dual edge 4. falling edge latching 1 st pixel 5. de-skewing enabled to 100 6. high voltage swing connect d[23:12] to vga source stuff only r1, r2, r6 stuff only r8, r13, r14, r11 stuff only r17 1. 24 bit 2. single clock 3. single edge 4. falling edge 5. de-skewing disabled 6. high voltage swing. connect d[23:12] to vga source stuff only r1, r5, r6 stuff only r12, r13, r14, r15 stuff only r17 1. 12 bit 2 2. single clock 3. dual edge 4. rising edge of idck+ latching 1 st ? pixel 5. de-skewing disabled 6. high voltage swing. ground d[23:12] stuff only r4, r2, r3 stuff only r12, r13, r14, r15 stuff only r17 1. 12 bit 3 2. dual clock 3. dual edge, 4. falling edge of idck+ latching 1 st ? pixel 5. de-skewing enabled to 100 6. low swing mode ground d[23:12] stuff only r4, r5, r6 stuff only r8, r13, r14, r11 stuff only r18, r19 notes 1. in 24 bit idck+ is input clock. idck- should be tied to ground. 2. in 12 bit dual edge mode, idck- is not used. 3. this setting is equivalent to dvo mode. in dvo mode both idck+ and idck- must be connected. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 21 sii -ds-0021-d tft panel data mapping the following tft data mapping tables are strictly listed for single link tft applications only. sii 143b, sii 151b, sii 153b and sii 161b all have the same pinout. as such mapping will be the same when sii 143b or sii 151b or sii 153b is used in place of sii 161b. table 4. one pixel/clock input/output tft mode - vesa p&d and fpdi-2 compliant tft vga output tx input data rx output data tft panel input 24-bpp 18-bpp 160 164 161b 141b 24-bpp 18-bpp b0 die0 d0 qe0 q0 b0 b1 die1 d1 qe1 q1 b1 b2 b0 die2 d2 qe2 q2 b2 b0 b3 b1 die3 d3 qe3 q3 b3 b1 b4 b2 die4 d4 qe4 q4 b4 b2 b5 b3 die5 d5 qe5 q5 b5 b3 b6 b4 die6 d6 qe6 q6 b6 b4 b7 b5 die7 d7 qe7 q7 b7 b5 g0 die8 d8 qe8 q8 g0 g1 die9 d9 qe9 q9 g1 g2 g0 die10 d10 qe10 q10 g2 g0 g3 g1 die11 d11 qe11 q11 g3 g1 g4 g2 die12 d12 qe12 q12 g4 g2 g5 g3 die13 d13 qe13 q13 g5 g3 g6 g4 die14 d14 qe14 q14 g6 g4 g7 g5 die15 d15 qe15 q15 g7 g5 r0 die16 d16 qe16 q16 r0 r1 die17 d17 qe17 q17 r1 r2 r0 die18 d18 qe18 q18 r2 r0 r3 r1 die19 d19 qe19 q19 r3 r1 r4 r2 die20 d20 qe20 q20 r4 r2 r5 r3 die21 d21 qe21 q21 r5 r3 r6 r4 die22 d22 qe22 q22 r6 r4 r7 r5 die23 d23 qe23 q23 r7 r5 shift clk shift clk idck idck odck odck shift clk shift clk vsync vsync vsync vsync vsync vsync vsync vsync hsync hsync hsync hsync hsync hsync hsync hsync de de de de de de de de for 18-bit mode, the flat panel graphics controller interfaces to the transmitter exactly the same as in the 24-bit mode; however, 6 bits per channel (color) are used instead of 8. it is recommended that unused data bits be tied low. as can be seen from the above table, the data mapping for less than 24-bit per pixel interfaces are msb justified. the data is sent during active display time while the control signals are sent during blank time. note that the three data channels (ch0, ch1, ch2) are mapped to blue, green and red data respectively. www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 22 table 5. 24-bit one pixel/clock input with 24-bit two pixels/clock output tft mode tft vga output tx input data rx output data tft panel input 24-bpp 160 164 161b 24-bpp b0 die0 d0 qe0 b0 - 0 b1 die1 d1 qe1 b1 - 0 b2 die2 d2 qe2 b2 - 0 b3 die3 d3 qe3 b3 - 0 b4 die4 d4 qe4 b4 - 0 b5 die5 d5 qe5 b5 - 0 b6 die6 d6 qe6 b6 - 0 b7 die7 d7 qe7 b7 - 0 g0 die8 d8 qe8 g0 - 0 g1 die9 d9 qe9 g1 - 0 g2 die10 d10 qe10 g2 - 0 g3 die11 d11 qe11 g3 - 0 g4 die12 d12 qe12 g4 - 0 g5 die13 d13 qe13 g5 - 0 g6 die14 d14 qe14 g6 - 0 g7 die15 d15 qe15 g7 - 0 r0 die16 d16 qe16 r0 - 0 r1 die17 d17 qe17 r1 - 0 r2 die18 d18 qe18 r2 - 0 r3 die19 d19 qe19 r3 - 0 r4 die20 d20 qe20 r4 - 0 r5 die21 d21 qe21 r5 - 0 r6 die22 d22 qe22 r6 - 0 r7 die23 d23 qe23 r7 - 0 qo0 b0 - 1 qo1 b1 - 1 qo2 b2 - 1 qo3 b3 - 1 qo4 b4 - 1 qo5 b5 - 1 qo6 b6 - 1 qo7 b7 - 1 qo8 g0 - 1 qo9 g1 - 1 qo10 g2 - 1 qo11 g3 - 1 qo12 g4 - 1 qo13 g5 - 1 qo14 g6 - 1 qo15 g7 - 1 qo16 r0 - 1 qo17 r1 - 1 qo18 r2 - 1 qo19 r3 - 1 qo20 r4 - 1 qo21 r5 - 1 qo22 r6 - 1 qo23 r7 - 1 shift clk idck idck odck shift clk/2 vsync vsync vsync vsync vsync hsync hsync hsync hsync hsync de de de de de www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 23 sii -ds-0021-d table 6. 18-bit one pixel/clock input with 18-bit two pixels/clock output tft mode tft vga output tx input data tx output data tft panel input 18-bpp 160 164 161b 141b 18-bpp die0 d0 qe0 die1 d1 qe1 b0 die2 d2 qe2 q0 b0 - 0 b1 die3 d3 qe3 q1 b1 - 0 b2 die4 d4 qe4 q2 b2 - 0 b3 die5 d5 qe5 q3 b3 - 0 b4 die6 d6 qe6 q4 b4 - 0 b5 die7 d7 qe7 q5 b5 - 0 die8 d8 qe8 die9 d9 qe9 g0 die10 d10 qe10 q6 g0 - 0 g1 die11 d11 qe11 q7 g1 - 0 g2 die12 d12 qe12 q8 g2 - 0 g3 die13 d13 qe13 q9 g3 - 0 g4 die14 d14 qe14 q10 g4 - 0 g5 die15 d15 qe15 q11 g5 - 0 die16 d16 qe16 die17 d17 qe17 r0 die18 d18 qe18 q12 r0 - 0 r1 die19 d19 qe19 q13 r1 - 0 r2 die20 d20 qe20 q14 r2 - 0 r3 die21 d21 qe21 q15 r3 - 0 r4 die22 d22 qe22 q16 r4 - 0 r5 die23 d23 qe23 q17 r5 - 0 qo0 qo1 qo2 q18 b0 - 1 qo3 q19 b1 - 1 qo4 q20 b2 - 1 qo5 q21 b3 - 1 qo6 q22 b4 - 1 qo7 q23 b5 - 1 qo8 qo9 qo10 q24 g0 - 1 qo11 q25 g1 - 1 qo12 q26 g2 - 1 qo13 q27 g3 - 1 qo14 q28 g4 - 1 qo15 q29 g5 - 1 qo16 qo17 qo18 q30 r0 - 1 qo19 q31 r1 - 1 qo20 q32 r2 - 1 qo21 q33 r3 - 1 qo22 q34 r4 - 1 qo23 q35 r5 - 1 shift clk idck idck odck shift clk/2 shift clk/2 vsync vsync vsync vsync vsync vsync hsync hsync hsync hsync hsync hsync de de de de de de www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 24 design recommendations 1.5v to 3.3v i 2 c bus level-shifting to program the sii 164 via i 2 c mode sda and scl swing level must be 3.3v. dvo sources have i 2 c swing of 1.5v. to ensure proper initialization of the sii 164 a bi-directional voltage level-shifting circuit between the sii 164 i 2 c bus and the vga or driving source should be implemented. two suggested components that can be used to achieve this is by using either a dual n-channel transistor like fairchild semiconductor?s ndc7002n or the philips gtl2010 high speed bus switch. refer to figure 16 for a schematic example using a dual n-channel transistor for translating an i 2 c 1.5v signal to 3.3v i 2 c signal and vice versa. 1.5v 1.5v 1k 1.5v i 2 c data from vga 2.2k 2.9v 3.3v 1k g s d q2 2n7002 3 1 2 1.5v i 2 c clk from vga 3.3v 2.9v 3.3v i 2 c clk to sii 164 2.2k 3.3v i 2 c data to sii 164 g s d q4 2n7002 3 1 2 figure 16. i 2 c bus voltage level-shifting using fairchild ndc7002n figure 17 illustrates a schematic example using the philips gtl 2010 to achieve a 1.5v to 3.3v bi-directional level-shift. 1.5v i 2 c data from vga r1 1k 3.3v i 2 c data to sii 164 r4 2.2k r5 2.2k 3.3v i 2 c clk to sii 164 3.3v r3 200k 1.5v r2 1k 5v 1.5v i 2 c clk from vga u1 gtl2010 1 2 3 4 24 23 22 21 20 19 18 17 16 15 14 13 5 6 7 8 9 10 11 12 gnd sref s1 s2 gref dref d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 s3 s4 s5 s6 s7 s8 s9 s10 figure 17. i 2 c bus voltage level shifting using philips gtl 2010 www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 25 sii -ds-0021-d voltage ripple regulation the power supply to pvcc is very important to the proper operation of the transmitter chips. pvcc does not draw much current so any voltage regulator that can supply 50ma or more is sufficient. two suggested voltage regulators are tl431 from texas instruments or lm317 from national semiconductor. two examples are shown in figure 18 and figure 19 v in (5v) v out (3.3v) to pvcc1 and pvcc2 tl431 100-150 ohms 1k ohms 1% 3k ohms 1% v ref cathode anode ref figure 18. voltage regulation using tl431 decoupling and bypass capacitors are also involved with power supply connections, as described in detail in figure 20 and figure 21. v out (3.3v) to pvcc1 and pvcc2 v in (5v) 240 ohms 390 ohms v in v out adj lm317emp figure 19. voltage regulation using lm317 www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 26 decoupling capacitors designers should include decoupling and bypass capacitors at each power pin in the layout. these are shown schematically in figure 21. place these components as closely as possible to the sii 164 pins, and avoid routing through vias if possible, as shown in figure 20, which is representative of the various types of power pins on the transmitter. c1 vcc ferrite via to gnd vcc gnd c2 c3 l1 figure 20. decoupling and bypass capacitor placement vccpin c1 c2 l1 c3 vcc figure 21. decoupling and bypass schematic the values shown in table 7 are recommendations that should be adjusted according to the noise characteristics of the specific board-level design. pins in one group (such as vcc) may share c2, l1, and c3, each pin having c1 placed as closely to the pin as possible. table 7. recommended components for bypass and decoupling circuits c1 c2 c3 l1 100 ? 300 pf 2.2 ? 10 f 10 f 200+ ? www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 27 sii -ds-0021-d series damping resistors on outputs series resistors are effective in lowering the data-related emissions and reducing reflections. series resistors with suggested value of 22 ? or 33 ? should be placed close to the output pins of the vga source or graphics chip, as shown in figure 22. d[23..0] vga figure 22. series input damping resistors for driving source differential trace routing the routing for the sii 164 chip is relatively simple since no spiral skew compensation is needed. however, a few small precautions are required to achieve the full performance and reliability of dvi. the transmitter can be placed fairly far from the output connector, but care should be taken to route each differential signal pair together and achieve impedance of 100 ? between the differential signal pair. however, note that the longer the differential traces are between the transmitter and the output connector, the higher the chance that external signal noise will couple onto the low-voltage signals and affect image quality. do not split or have asymmetric trace routing between the differential signal pair. vias are very inductive and can cause phase delay problems if applied unevenly within a differential pair. vias should be minimized or avoided if possible by placing all differential traces on the top layer of the pcb. figure 23 illustrates an incorrect routing of the differential signal from the sii 164 to the dvi connector. figure 24 illustrates the correct method to route the differential signal from the sii 164 to the dvi connector. figure 25 illustrates recommended routing for differential traces at the dvi connector. tx figure 23. example of incorrect differential signal routing www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 28 tx figure 24. example of correct differential signal routing txc- txc+ tx0- tx0+ tx1- tx1+ tx2- tx2+ 1 8 9 16 17 24 figure 25. differential trace routing to dvi connector(top side view) www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet 29 sii -ds-0021-d package dimensions and marking specification ddddddddd llllll.llll yyww x.xx device # lot # date code sii rev. # e1 f1 d1 g1 a2 a1 e b l1 c jedec package code ms026-aed-hd typ max a thickness 1.20 a1 stand-off 0.15 a2 body thickness 1.00 1.05 d1 body size 8.00 e1 body size 10.00 f1 footprint 12.00 g1 footprint 12.00 l1 lead length 1.00 b lead width 0.22 c lead thickness 0.20 e lead pitch 0.50 dimensions in millimeters. overall thickness a=a1+a2. device device number ddddddddd standard sii164ct64 pb-free sii164ctg64 legend description llllll.llll lot number yy year of mfr ww work week of mfr. x.xx revision figure 26. 64-pin tqfp package dimensions (jedec code ms-026ed) ordering information standa r d pa r t nu m be r : si i 164 c t 64 pb-free part number: sii 164ctg64('g' designates pb-free packaging) www.datasheet.co.kr datasheet pdf - http://www..net/
sii 164 panellink transmitter data sheet sii -ds-0021-d 30 ? 2002 silicon image. inc. 09/02 sii - ds-0021-d silicon image, inc. tel: (408) 616-4000 1060 e. arques avenue fax: (408) 830-9530 sunnyvale, ca 94085 e-mail: salessupport@siimage.com usa web: www.siliconimage.com www.datasheet.co.kr datasheet pdf - http://www..net/

▲Up To Search▲

Price & Availability of SIL164

	To Download SIL164 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .